The speed of execution by a microprocessor of an instruction requiring an addition or subtraction is limited by the speed of operation of the adder within the ALU. The adder is primarily limited in speed by the propagation delay between the carry input of the least significant bit (LSB) of the adder to the carry output of the most significant bit (MSB) of the adder. Thus, the carry in to carry out propagation delays across the bits of the adder are cumulative whereby the carry in to carry out path is said to constitute the "worst case" path for propagation delay. In contrast, the propagation delay from the inputs of each adder bit to the sum output of the bit is not cumulative and, accordingly, does not pose the same delay problem.
Due to the cumulative effect of the propagation delays between the carry in and carry out lines of the adder bits, the execution of a microprocessor instruction which requires an addition or subtraction operation typically requires an extra or so-called "dead" machine cycle.
The problem solved by the present invention is that of accelerating the speed at which the ALU adder operates so as to eliminate the need for a "dead" cycle in executing microprocessor instructions.